Викладено класичні принципи організації та дизайну для основних блоків комп'ютерів. Розкрито проблеми організації та проектування блоків процесора. Подано інформацію про класичні принципи організації комп'ютера та дизайну. Матеріали подано англійською мовою.

An approach to the synthesis of adaptive structures represented by multi-level logic, Boolean network described as an acyclic graph with universal logical elements, is proposed. As a result of the synthesis of such structures are determined the type of logic function of the Boolean network of a given learning sample of binary vectors, which allows using of this structure for the problem of classification of input vectors. Unlike known methods for the synthesis of multilevel logic, method of the synthesis of such schemes proposed in this paper. It based on the description of a Boolean network by Zhegalkin's polynomials, starting from subnet (n = 3).

Abstract - A hardware implementation of pseudorandom bit generator based on FPGA chips, which use the principle of reconfigurability that allows the modernization of their algorithms and on-line replacement of the internal structure (reconfiguration) in the process of functioning have been considered in the paper. Available DSP blocks embedded into the structure of FPGA chips allow efficient hardware implementation of the pseudorandom bit generator through the implementation of the basic operations of multiplication with accumulation on the gate level. Using CAD ISE 14.02 Foundation and VHDL language three types of pseudo-random bit generators have been implemented on Spartan series chip 6SLX4CSG225-3, for which time and hardware expenses are represented. Using the simulating system ModelSim SE 10.1c, timing diagrams of simulation for these structures have been obtained.